Semiconductor devices, and especially integrated circuits, are very sensitive to BSD events that can cause serious degradation or damage of the IC. Solutions known in the art that protect internal elements of the IC from damage are based on circuits that shunt the ESD current between the IC power supply rails.
One of the circuits known in the art protects a power supply rail from positive ESD events referenced to a grounded power supply rail. The circuit consist of a trigger circuit, an inverter stage, and a large NMOSFET transistor. Trigger circuit is designed as a resistor-capacitor (RC) transient detector. In response to an ESD event that induces a rapid positive voltage transient on the power supply rail, trigger circuit initially holds a middle node of RC trigger circuit well below grounded power supply rail. The inverter stage then drives the gate of NMOSFET. Once turned on, NMOSFET transistor provides a low resistance shunt between the power rail and the grounded rail. NMOSFET transistor will remain conductive for a period of time, which is determined by the RC time constant of the trigger circuit. It is critical that this RC time constant is long enough to exceed the maximum expected duration of an ESD event, typically a few hundred nanoseconds, while short enough to avoid false triggering of the clamp circuit during normal ramp-up of the power rail, typically a few milliseconds. During normal operation of the IC, with a constant power supply level, NMOSFET is biased in a nonconductive state.
Since the resistor in the RC chain is NWELL resistor and the capacitor is MOS capacitor the described circuit has a number of disadvantages including the following:                huge size of the NWELL resistor,        temperature dependency of resistance of NWELL resistor, which results in false triggering of the circuit.        
Attempts at replacing NWELL resistor with smaller PMOSFET have failed since they could not exclude false clamp triggering in power up conditions. Up to 0.5V (threshold of PMOSFET) on power supply rail the PMOSFET does not conduct and voltage at middle node of RC chain does not rise and the threshold of the inverter in the clamp preamplifier exceeds voltage at middle node of RC trigger circuit for time enough for false clamp triggering.
Hence, considering the above disadvantages, an improved circuit for ESD protection is needed. The new circuit should be smaller and more reliable.